Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links
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Publication:834939
DOI10.1016/j.ipl.2004.08.005zbMath1173.68397OpenAlexW2169603675MaRDI QIDQ834939
Bimal K. Roy, Amiya Nayak, Soumen Maity
Publication date: 27 August 2009
Published in: Information Processing Letters (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/j.ipl.2004.08.005
Nonnumerical algorithms (68W05) Reliability, testing and fault tolerance of networks and computer systems (68M15)
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Cites Work
- Counting the number of fault patterns in redundant VLSI arrays
- Catastrophic faults in reconfigurable systolic linear arrays
- On enumeration of catastrophic fault patterns
- Wafer-Scale Integration of Systolic Arrays
- Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
- On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy