Wafer-Scale Integration of Systolic Arrays

DOI10.1109/TC.1985.1676584MaRDI QIDQ3347792zbMATH OpenOpenAlexFDO

Authors Tom Leighton, Charles E. Leiserson

Publication date 1985

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1985.1676584

zbMATH Keywords

fault-tolerant systemsspanning treeVLSIprobabilistic analysistraveling salesman

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80) Applications of graph theory to circuits and networks (94C15) Theory of software (68N99)

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(16)

• Synthesis, structure and power of systolic computations
• Lessa: an array to solve a aet of linear equations
• Fast geometric approximation techniques and geometric embedding problems
• Fault-tolerance VLSI sorters
• Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links
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• Tight bounds for minimax grid matching with applications to the average case analysis of algorithms
• On the complexity of wafer-to-wafer integration
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• Approximation algorithms for the wafer to wafer integration problem
• The average-case analysis of some on-line algorithms for bin packing
• A framework for solving VLSI graph layout problems
• Catastrophic faults in reconfigurable systolic linear arrays
• Tolerating faults in a mesh with a row of spare nodes
• Scaling and Integration of High-Speed Electronics and Optomechanical Systems
• On the design of reliable Boolean circuits that contain partially unreliable gates

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