Wafer-Scale Integration of Systolic Arrays

DOI10.1109/TC.1985.1676584zbMath0558.94020OpenAlexW2046826146MaRDI QIDQ3347792

Leighton, Tom, Charles E. Leiserson

Publication date: 1985

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1985.1676584

zbMATH Keywords

traveling salesmanprobabilistic analysisspanning treeVLSIfault-tolerant systems

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80) Applications of graph theory to circuits and networks (94C15) Theory of software (68N99)

Related Items (11)

Tolerating faults in a mesh with a row of spare nodes ⋮ Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links ⋮ The average-case analysis of some on-line algorithms for bin packing ⋮ Fault-tolerance VLSI sorters ⋮ Catastrophic faults in reconfigurable systolic linear arrays ⋮ On the design of reliable Boolean circuits that contain partially unreliable gates ⋮ Synthesis, structure and power of systolic computations ⋮ Lessa: an array to solve a aet of linear equations ⋮ Fast geometric approximation techniques and geometric embedding problems ⋮ Tight bounds for minimax grid matching with applications to the average case analysis of algorithms ⋮ A framework for solving VLSI graph layout problems

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