Wafer-Scale Integration of Systolic Arrays
From MaRDI portal
Publication:3347792
DOI10.1109/TC.1985.1676584zbMATH Open0558.94020OpenAlexW2046826146MaRDI QIDQ3347792FDOQ3347792
Authors: Tom Leighton, Charles E. Leiserson 
Publication date: 1985
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tc.1985.1676584
Recommendations
Cellular automata (computational aspects) (68Q80) Applications of graph theory to circuits and networks (94C15) Theory of software (68N99)
Cited In (16)
- Synthesis, structure and power of systolic computations
- Lessa: an array to solve a aet of linear equations
- Fast geometric approximation techniques and geometric embedding problems
- Fault-tolerance VLSI sorters
- Title not available (Why is that?)
- Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links
- Tight bounds for minimax grid matching with applications to the average case analysis of algorithms
- On the complexity of wafer-to-wafer integration
- On the complexity of wafer-to-wafer integration
- Approximation algorithms for the wafer to wafer integration problem
- The average-case analysis of some on-line algorithms for bin packing
- A framework for solving VLSI graph layout problems
- Catastrophic faults in reconfigurable systolic linear arrays
- Tolerating faults in a mesh with a row of spare nodes
- Scaling and Integration of High-Speed Electronics and Optomechanical Systems
- On the design of reliable Boolean circuits that contain partially unreliable gates
This page was built for publication: Wafer-Scale Integration of Systolic Arrays
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3347792)
