Modular Matrix Multiplication on a Linear Array

DOI10.1109/TC.1984.1676369zbMATH Open0544.68029OpenAlexW2041650442MaRDI QIDQ3334071FDOQ3334071

Authors: I. V. Ramakrishnan, Peter J. Varman 

Publication date: 1984

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1984.1676369

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zbMATH Keywords

parallel processingVLSIarray processorsmatrix multiplication algorithm on a linear array of processing elements

Mathematics Subject Classification ID

Algorithms in computer science (68W99) Theory of operating systems (68N25)

Cited In (13)

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• Exploiting Linearity of Modular Multiplication
• On high-speed computing with a programmable linear array
• Parallel algorithms and architectures for matrix multiplication
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• A Robust Matrix-Multiplication Array
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• Optimal geometric algorithms for digitized images on fixed-size linear arrays and scan-line arrays
• A modular systolic linear array for gaussian elimination
• An algorithm for multiplication of concatenated matrices
• Charge-mode parallel architecture for vector-matrix multiplication
• Complexity of matrix product on modular linear systolic arrays for algorithms with affine schedules

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