A methodology for algorithm regularization and mapping into time-optimal VLSI arrays

DOI10.1016/0167-8191(93)90104-SMaRDI QIDQ1208500zbMATH OpenFDO

Authors S. Singh, Hassan Barada, Ahmed El-Amawy

Publication date 16 May 1993

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(93)90104-S

zbMATH Keywords

algorithmic transformationsgraph methodology for regularizing data flowmappingsystolic architecturesystolic directed graphsystolic implementationsystolic precedence diagramtime-optimal VLSI arrays

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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