Automatic design and partitioning of systolic/wavefront arrays for VLSI

DOI10.1007/BF01602099zbMATH Open0647.68027OpenAlexW2007109040MaRDI QIDQ1104739FDOQ1104739

Authors: Harry W. Nelis, E. F. A. Deprettere 

Publication date: 1988

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01602099

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zbMATH Keywords

signal processingVLSIsystolic/wavefront arrays

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80) Theory of operating systems (68N25)

Cites Work

• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
• Title not available (Why is that?)
• Title not available (Why is that?)
• Automatic design and partitioning of systolic/wavefront arrays for VLSI

Cited In (7)

• Title not available (Why is that?)
• COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL
• Automatic design and partitioning of systolic/wavefront arrays for VLSI
• Title not available (Why is that?)
• Title not available (Why is that?)
• Title not available (Why is that?)
• Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming

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