Automatic design and partitioning of systolic/wavefront arrays for VLSI

DOI10.1007/BF01602099MaRDI QIDQ1104739zbMATH OpenOpenAlexFDO

Authors Harry W. Nelis, E. F. A. Deprettere

Publication date 1988

Published in Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf01602099

zbMATH Keywords

signal processingsystolic/wavefront arraysVLSI

Mathematics Subject Classification ID

Theory of operating systems (68N25) Cellular automata (computational aspects) (68Q80)

Review text

We show how systolic/wavefront arrays can be automatically designed and partitioned to solve problems of arbitrary size. Buffer memory and control of a resulting array is regular and simple, and is generated automatically. Also, the throughput of the arrays is matched with the I/0 speed of the host to which it is to be attached. The approach strongly relies upon classical concepts in signal processing, such as signal flow graphs and state transition functional behaviour. Some illustrative examples are included.

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Cites work

• Automatic design and partitioning of systolic/wavefront arrays for VLSI
• scientific article; zbMATH DE number 3968510 (Why is no real title available?)
• scientific article; zbMATH DE number 3628373 (Why is no real title available?)
• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays

Cited in

(7)

• Automatic design and partitioning of systolic/wavefront arrays for VLSI
• COMBINING BACKGROUND MEMORY MANAGEMENT AND REGULAR ARRAY CO-PARTITIONING, ILLUSTRATED ON A FULL MOTION ESTIMATION KERNEL
• scientific article; zbMATH DE number 3968510 (Why is no real title available?)
• scientific article; zbMATH DE number 4078817 (Why is no real title available?)
• scientific article; zbMATH DE number 4082984 (Why is no real title available?)
• scientific article; zbMATH DE number 2217830 (Why is no real title available?)
• Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming

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