Automatic design and partitioning of systolic/wavefront arrays for VLSI (Q1104739)

We show how systolic/wavefront arrays can be automatically designed and partitioned to solve problems of arbitrary size. Buffer memory and control of a resulting array is regular and simple, and is generated automatically. Also, the throughput of the arrays is matched with the I/0 speed of the host to which it is to be attached. The approach strongly relies upon classical concepts in signal processing, such as signal flow graphs and state transition functional behaviour. Some illustrative examples are included.