Polymorphic arrays: A novel VLSI layout for systolic computers (Q1088396)

This paper proposes a novel architecture for massively parallel systolic computers, which is based on results from lattice theory. In the proposed architecture, each processor is connected to four other processors via constant-length wires in a regular borderless pattern. The mapping of processes to processors is continuous, and the architecture guarantees exceptional load uniformity for rectangular process arrays of arbitrary sizes. In addition, no time-sharing is ever required when the ratio of processes to processors is smaller than 1/\(\sqrt{5}\).