Polymorphic arrays: A novel VLSI layout for systolic computers
From MaRDI portal
Publication:1088396
DOI10.1016/0022-0000(86)90042-5zbMath0612.68005OpenAlexW2076568053MaRDI QIDQ1088396
Publication date: 1986
Published in: Journal of Computer and System Sciences (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/0022-0000(86)90042-5
Related Items (5)
Polymorphic arrays: A novel VLSI layout for systolic computers ⋮ Two dimensional range minimum queries and Fibonacci lattices ⋮ MPC-in-multi-heads: a multi-prover zero-knowledge proof system (or: how to jointly prove any NP statements in ZK) ⋮ How to find a battleship ⋮ Tight bounds for minimax grid matching with applications to the average case analysis of algorithms
Cites Work
This page was built for publication: Polymorphic arrays: A novel VLSI layout for systolic computers