A systolic array with applications to image processing and wire-routing in VLSI circuits

DOI10.1016/S0167-8191(05)80020-1zbMATH Open0723.68009OpenAlexW1971505705MaRDI QIDQ757007FDOQ757007

Authors: D. Kharzeev 

Publication date: 1991

Published in: Parallel Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0167-8191(05)80020-1

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zbMATH Keywords

image processingmorphologycircuit layout

Mathematics Subject Classification ID

Circuits, networks (94C99) Computing methodologies for image processing (68U10) General theory of computer systems (68M01)

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• Polymorphic arrays: A novel VLSI layout for systolic computers
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• A VLSI systolic architecture for solving DBT-transformed fuzzy clustering problems of arbitrary size
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• Systolic architectures for vector quantization
• A systolic LRU processor and its top-down development

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