A systolic array with applications to image processing and wire-routing in VLSI circuits

DOI10.1016/S0167-8191(05)80020-1MaRDI QIDQ757007zbMATH OpenOpenAlexFDO

Authors D. Kharzeev

Publication date 1991

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0167-8191(05)80020-1

zbMATH Keywords

circuit layoutimage processingmorphology

Mathematics Subject Classification ID

General theory of computer systems (68M01) Computing methodologies for image processing (68U10) Circuits, networks (94C99)

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(27)

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• A simplified design strategy for mapping image processing algorithms on a SIMD torus
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• A VLSI systolic architecture for solving DBT-transformed fuzzy clustering problems of arbitrary size
• A programmable systolic device for image processing based on mathematical morphology

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