A bit-level systolic array for digital contour smoothing

DOI10.1016/0167-8191(89)90088-4MaRDI QIDQ583841zbMATH OpenOpenAlexFDO

Authors N. Petkov, Fridrich Sloboda

Publication date 1989

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(89)90088-4

zbMATH Keywords

circulant Toeplitz matricesdigital contour smoothinginner product step processorsleast-squareslinear systolic arrayVLSI implementation

Mathematics Subject Classification ID

Numerical smoothing, curve fitting (65D10) Numerical solutions to overdetermined systems, pseudoinverses (65F20) Theory of operating systems (68N25)

Review text

A family of linear operators (defined by circulant Toeplitz matrices) for digital contour smoothing in the sense of least-squares is described. In order to ensure a real time computation a two-way linear systolic array of inner product step processors is proposed. The structure of this array allows to implement each operator of the family. For a particular operator, by taking advantage of an appropriate decomposition of the circulant Toeplitz matrix, a systolic design for the basic inner product step processor is presented so that a bit-level implementation of this operator is obtained and the multiplication is performed by shifting operations. The nice features of the proposed systolic algorithm make it quite suitable for VLSI implementation.

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