A systolic LRU processor and its top-down development

DOI10.1016/0167-6423(90)90087-TMaRDI QIDQ2639645zbMATH OpenOpenAlexFDO

Authors Yanyan Li

Publication date 1990

Published in Science of Computer Programming (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-6423(90)90087-t

zbMATH Keywords

systolic systemsLRU processormulti-level storage systems

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80) Theory of data (68P99) Computer system organization (68M99)

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Cited in

(2)

• H-NMRU: An efficient cache replacement policy with low area
• Correct translation of data parallel assignment onto array processors

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