Minimizing buffer requirements under rate-optimal schedule in regular dataflow networks

DOI10.1023/A:1015452903532MaRDI QIDQ1851173zbMATH OpenOpenAlexFDO

Authors Yanyan Li, Rama Govindarajan, Guang R. Gao, P. Desai

Publication date 15 December 2002

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1015452903532

zbMATH Keywords

buffer minimizationdataflow graphsDigital Signal Processing (DSP) computationMulti-Rate Software PipeliningRegular Stream Flow Graphs,software pipelining

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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