Model checking reconfigurable Petri nets with Maude

DOI10.1007/978-3-319-40530-8_4MaRDI QIDQ3187803zbMATH OpenOpenAlexFDO

Authors A. Schulz, J. Padberg

Publication date 5 September 2016

Published in Graph Transformation (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-319-40530-8_4

zbMATH Keywords

dynamic partial reconfigurationfield programmable gate arrayMaudemodel checkingreconfigurable Petri netsrewrite logic

Mathematics Subject Classification ID

Grammars and rewriting systems (68Q42) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

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Cites work

• A rewriting-based model checker for the linear temporal logic of rewriting
• scientific article; zbMATH DE number 1973125 (Why is no real title available?)
• scientific article; zbMATH DE number 1982209 (Why is no real title available?)
• scientific article; zbMATH DE number 1751901 (Why is no real title available?)
• scientific article; zbMATH DE number 5585443 (Why is no real title available?)
• Independence of Net Transformations and Token Firing in Reconfigurable Place/Transition Systems
• Lectures on Concurrency and Petri Nets
• Model checking reconfigurable Petri nets with Maude
• The Maude LTL model checker

Cited in

(11)

• A process calculus BigrTiMo of mobile systems and its formal semantics
• \textsc{AdamMC}: a model checker for Petri nets with transits against Flow-LTL
• Model checking Petri nets with MSVL
• Model checking reconfigurable Petri nets with Maude
• scientific article; zbMATH DE number 2114135 (Why is no real title available?)
• Automated Technology for Verification and Analysis
• A Non-Deterministic Multiset Query Language
• Modular rewritable Petri nets: an efficient model for dynamic distributed systems
• Canonization of reconfigurable PT nets in \texttt{Maude}
• Symbolic analysis and parameter synthesis for time Petri nets using Maude and SMT solving
• A rewriting-logic-with-SMT-based formal analysis and parameter synthesis framework for parametric time Petri nets

Describes a project that uses

Uses Software

• SPIN

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