Optimizing database architecture for the new bottleneck: memory access
In the past decade, advances in the speed of commodity CPUs have far out-paced advances in memory latency. Main-memory access is therefore increasingly a performance bottleneck for many computer applications, including database systems. In this article, we use a simple scan test to show the severe impact of this bottleneck. The insights gained are translated into guidelines for database architecture, in terms of both data structures and algorithms. We discuss how vertically fragmented data structures optimize cache performance on sequential data access. We then focus on equi-join, typically a random-access operation, and introduce radix algorithms for partitioned hash-join. The performance of these algorithms is quantified using a detailed analytical model that incorporates memory access cost. Experiments that validate this model were performed on the Monet database system. We obtained exact statistics on events such as TLB misses and L1 and L2 cache misses by using hardware performance counters found in modern CPUs. Using our cost model, we show how the carefully tuned memory access pattern of our radix algorithms makes them perform well, which is confirmed by experimental results.
- High-Performance Operations Using a Compressed Database Architecture
- Data page layouts for relational databases on deep memory hierarchies
- scientific article; zbMATH DE number 2090630
- An efficient B\(^{+}\)-tree design for main-memory database systems with strong access locality
- scientific article; zbMATH DE number 176491
- Data page layouts for relational databases on deep memory hierarchies
- High-Performance Operations Using a Compressed Database Architecture
- scientific article; zbMATH DE number 1487625 (Why is no real title available?)
- Body fitted link-cell algorithm for particulate flow simulation in curved pipeline domain
- An efficient cache conscious multi-dimensional index structure
This page was built for publication: Optimizing database architecture for the new bottleneck: memory access
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1606846)