Parallel and serial concatenated single parity check product codes

DOI10.1155/ASP.2005.775MaRDI QIDQ2570489zbMATH OpenFDO

Authors David M. Rankin, T. Aaron Gulliver, Desmond P. Taylor

Publication date 28 October 2005

Published in EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1155/ASP.2005.775

zbMATH Keywords

parallel and serial concatenationsingle parity-check product codes

Mathematics Subject Classification ID

Prefix, length-variable, comma-free codes (94A45)

Review text

Summary: The parallel and serial concatenation of codes is well established as a practical means of achieving excellent performance. In this paper, we introduce the parallel and serial concatenation of single parity-check (SPC) product codes. The weight distribution of these codes is analyzed and the performance is bounded. Simulation results confirm these bounds at high signal-to-noise ratios. The performance of these codes (and some variants) is shown to be quite good given the low decoding complexity and reasonably short blocklengths.

Recommendations

• Single parity check product codes
• Asymptotic performance of single parity-check product codes
• Concatenated Codes: Serial and Parallel
• Performance of Parallel Concatenated Coding Schemes
• Multiple accumulated-crossover parallel concatenated SPC codes

Cited in

(6)

• Multiple accumulated-crossover parallel concatenated SPC codes
• On the performance and implementation issues of interleaved single parity check turbo product codes
• Concatenated Codes: Serial and Parallel
• Asymptotic performance of single parity-check product codes
• Performance Analysis of Turbo-SPC Codes
• Single parity check product codes

This page was built for publication: Parallel and serial concatenated single parity check product codes

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2570489)