Partial-order model checking: A guide for the perplexed

DOI10.1007/3-540-55179-4_31MaRDI QIDQ6493551zbMATH OpenFDO

Authors David K. Probst, Hon F. Li

Publication date 29 April 2024

Full work available at URL https://doi.org/10.1007/3-540-55179-4_31

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cites work

• Compiling communicating processes into delay-insensitive VLSI circuits
• scientific article; zbMATH DE number 177236 (Why is no real title available?)
• Modeling concurrency with partial orders
• On the existence of delay-insensitive fair arbiters: Trace theory and its limitations
• Trace theory and VLSI design

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