Compiling communicating processes into delay-insensitive VLSI circuits
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(22)- Reflections on the future of concurrency theory in general and process calculi in particular
- Asynchronous datapaths and the design of an asynchronous adder
- Delay-insensitive pipelined communication on parallel buses
- CTRL: extension of CTL with regular expressions and fairness operators to verify genetic regulatory networks
- Reconciling fault-tolerant distributed computing and systems-on-chip
- A new explanation of the glitch phenomenon
- Verification of asynchronous circuits by BDD-based model checking of Petri nets
- Rewriting semantics of production rule sets
- scientific article; zbMATH DE number 3926249 (Why is no real title available?)
- A formal approach to designing delay-insensitive circuits
- Retargeting a hardware compiler using protocol converters
- scientific article; zbMATH DE number 3976939 (Why is no real title available?)
- Revisiting sequential composition in process calculi
- Asynchronous logic circuits and sheaf obstructions
- On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
- VLSI programming for the compact disc player
- Program refinement in fair transition systems
- Compositional verification of asynchronous concurrent systems using CADP
- Calculational derivation of a counter with bounded response time and bounded power dissipation
- Partial-order model checking: A guide for the perplexed
- On the susceptibility of QDI circuits to transient faults
- Elasticity and Petri Nets
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