Partial order reduction for deep bug finding in synchronous hardware

DOI10.1007/978-3-030-45190-5_20MaRDI QIDQ5039518zbMATH OpenOpenAlexFDO

Authors Makai Mann, Clark Barrett

Publication date 13 October 2022

Published in Tools and Algorithms for the Construction and Analysis of Systems (Search for Journal in Brave)

Copyright license Creative Commons Attribution 4.0 International

Full work available at URL https://doi.org/10.1007/978-3-030-45190-5_20

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Specification and verification (program logics, model checking, etc.) (68Q60)

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Cites work

• A methodology for hardware verification using compositional model checking
• A Practical Approach to Word Level Model Checking of Industrial Netlists
• Accelerating bounded model checking of safety properties
• An algorithmic approach for checking closure properties of temporal logic specifications and -regular languages
• Correct Hardware Design and Verification Methods
• Decision procedures. An algorithmic point of view. With foreword by Randal E. Bryant
• Handbook of model checking
• scientific article; zbMATH DE number 1670796 (Why is no real title available?)
• Interpolation and SAT-based model checking.
• Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique
• Peephole Partial Order Reduction
• SAT-Based Model Checking without Unrolling
• Symbolic model checking: \(10^{20}\) states and beyond

Describes a project that uses

Uses Software

• ABC
• Plingeling
• Boolector
• Lingeling
• Treengeling

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