ABC
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ABC Q24833
Cited in
(only showing first 100 items - show all)- CoSA
- Sally
- Btor2Tools
- GANAK
- Kissat
- Workcraft
- Compact and efficiently verifiable models for concurrent systems
- WALA
- On compiling Boolean circuits optimized for secure multi-party computation
- Shield synthesis
- Skolem functions for DQBF
- Improving characteristics of LUT-based mealy FSMs
- ESPRESSO
- Boolean functional synthesis: hardness and practical algorithms
- Improving the LUT count for mealy FSMS with transformation of output collections
- SPOT
- Scaling up livelock verification for network-on-chip routing algorithms
- TASTY
- VATA
- Solving SAT (and MaxSAT) with a quantum annealer: foundations, encodings, and preliminary results
- Automated and scalable verification of integer multipliers
- Incremental column-wise verification of arithmetic circuits using computer algebra
- RevKit
- Practical synthesis of reactive systems from LTL specifications via parity games
- STABLE
- Verifying chemical reaction network implementations: a pathway decomposition approach
- Cyclic-routing of unmanned aerial vehicles
- Unified QBF certification and its applications
- MTBDD
- QMDD
- Capo
- Advanced exact synthesis of Clifford+T circuits
- Wattch
- VeriCon
- Heuristic NPN classification for large functions using AIGs and LEXSAT
- The QBF Gallery: behind the scenes
- Labelled interpolation systems for hyper-resolution, clausal, and local proofs
- Automated formal analysis and verification: an overview
- Transalg
- SAT-Based Synthesis Methods for Safety Specs
- nuXmv
- Jimple
- Verifying deadlock-freedom of communication fabrics
- VS3
- Transfer of model checking to industrial practice
- Symbolic trajectory evaluation
- Antichains
- STEWord
- JKind
- Model checking data flows in concurrent network updates
- Encodings of bounded synthesis
- Sharemind
- SAT-Based Formula Simplification
- Chisel
- EnerJ
- ANaConDA
- Acacia+
- Z34Bio
- CAQE
- FlowDroid
- Rosette
- petBoss
- AIGER
- Mosel
- Yosys
- Anteater
- Strix
- Benchmarking a model checker for algorithmic improvements and tuning for performance
- AdamMC
- zUpdate
- Kuai
- FatTire
- tiny_sha3
- Visual DSD
- Ancilla-free synthesis of large reversible functions using binary decision diagrams
- scientific article; zbMATH DE number 7453178 (Why is no real title available?)
- Partial order reduction for deep bug finding in synchronous hardware
- Pyverilog
- Rewriting environment for arithmetic circuit verification
- Advanced Boolean techniques. Selected papers from the 13th international workshop on Boolean problems, Bremen, Germany, September 19--21, 2018
- Evaluating ESOP Optimization Methods in Quantum Compilation Flows
- Symbolic trajectory evaluation for word-level verification: theory and implementation
- Rely
- PolyCleaner
- RevSCA
- GenMul
- multgen
- VIS
- EPFL
- Owl
- Delag
- Frigate
- Oink
- RAReQS
- Pacheck
- Unbeast
- BoSy
- Verified cryptographic code for everybody
- A temporal logic for asynchronous hyperproperties
- Progress in certifying hardware model checking results
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