Rewriting environment for arithmetic circuit verification

DOI10.29007/RSWKMaRDI QIDQ5222992zbMATH OpenOpenAlexFDO

Authors Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej Ciesielski

Publication date 4 July 2019

Published in EPiC Series in Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.29007/rswk

zbMATH Keywords

arithmetic circuitscomputer algebraformal verification

Mathematics Subject Classification ID

Grammars and rewriting systems (68Q42) Specification and verification (program logics, model checking, etc.) (68Q60)

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(7)

• Designing arithmetic circuits by refinement in Ruby
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• Rewrite systems for integer arithmetic
• Reveal: A Formal Verification Tool for Verilog Designs

Describes a project that uses

Uses Software

• SINGULAR
• ABC
• STABLE

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