Symbolic trajectory evaluation for word-level verification: theory and implementation
DOI10.1007/S10703-017-0268-9zbMATH Open1360.68582OpenAlexW2588803340MaRDI QIDQ526779FDOQ526779
Authors: Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry 
Publication date: 15 May 2017
Published in: Formal Methods in System Design (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10703-017-0268-9
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hardware verificationSMT solvingsymbolic trajectory evaluationinvalid-bit encodingRTL verificationsymbolic simulationword-level verificationX-based abstraction
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- Symbolic trajectory evaluation for word-level verification: theory and implementation
- Correct Hardware Design and Verification Methods
Cited In (8)
- Verifying the implementation of an error control code
- A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL
- A Practical Approach to Word Level Model Checking of Industrial Netlists
- Matching multiplications in bit-vector formulas
- Efficient Automatic STE Refinement Using Responsibility
- Symbolic trajectory evaluation
- Explaining Symbolic Trajectory Evaluation by Giving It a Faithful Semantics
- Symbolic trajectory evaluation for word-level verification: theory and implementation
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