Performance analysis of a class of hierarchical hypercube multicomputer networks

DOI10.1016/0166-5316(91)90053-6MaRDI QIDQ3983059zbMATH OpenOpenAlexFDO

Authors Sivarama P. Dandamudi

Publication date 27 June 1992

Published in Performance Evaluation (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0166-5316(91)90053-6

zbMATH Keywords

fault-tolerancehierarchical networkhypercube

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Recommendations

• Fault-Tolerant Hierarchical Networks for Shared Memory Multiprocessors and their Bandwidth Analysis
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Cited in

(3)

• Analysis of hierarchical bus-based multicomputer architectures
• On the communication structures of hyper-ring and hypercube multicomputers
• A HIERARCHICAL MULTIPROCESSOR STRUCTURE BASED ON MULTISTAGE NETWORKS

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