Performance modeling and interpretive simulation of PIM architectures and applications

DOI10.1007/3-540-45706-2_19MaRDI QIDQ4813020zbMATH OpenFDO

Authors Zachary K. Baker, V. K. Prasanna Kumar

Publication date 12 August 2004

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2400/24000157.htm

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Recommendations

• The characterization of data intensive memory workloads on distributed PIM systems
• Adaptively mapping code in an intelligent memory architecture
• The Gilgamesh MIND processor-in-memory architecture for Petaflops-scale computing (extended abstract)
• Energy/performance design of memory hierarchies for processor-in-memory chips
• Memory management in a PIM-based architecture

Cited in

(5)

• A New Strategy to Improve the Performance of PDP-Systems Simulators
• The characterization of data intensive memory workloads on distributed PIM systems
• Energy/performance design of memory hierarchies for processor-in-memory chips
• The DIVA emulator: accelerating architecture studies for PIM-based systems
• An introduction to the Gilgamesh PIM architecture

This page was built for publication: Performance modeling and interpretive simulation of PIM architectures and applications

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4813020)