V. G. Chachanidze

Available identifiers

zbMath Open chachanidze.v-gMaRDI QIDQ1069665

List of research outcomes

Publication	Date of Publication	Type
Method of binary log-antilog evaluation in hardware for fast arithmetic- logical units. I	1985-01-01	Paper
Standby redundancy of finite automata in uniform computing arrays	1982-01-01	Paper
Redundancy of digital circuits in microcomputers	1981-01-01	Paper
Design of multifunctional cells in a rearrangeable multipurpose uniform computing array	1979-01-01	Paper
https://portal.mardi4nfdi.de/entity/Q4061968	1975-01-01	Paper

Research outcomes over time

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