Method of binary log-antilog evaluation in hardware for fast arithmetic- logical units. I

zbMATH Open0584.65006MaRDI QIDQ1069666FDOQ1069666

Authors: G. G. Asatiani, O. G. Smorodinova, V. G. Chachanidze 

Publication date: 1985

Published in: Automation and Remote Control (Search for Journal in Brave)

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zbMATH Keywords

error estimatesfast arithmetic-logical unitslogarithmic function

Mathematics Subject Classification ID

Computation of special functions and constants, construction of tables (65D20) Exponential and trigonometric functions (33B10)

Cited In (8)

• Division using a logarithmic-exponential transform to form a short reciprocal
• On the fast generation of base-k logarithm
• Interleaved memory function interpolators with application to an accurate LNS arithmetic unit
• Title not available (Why is that?)
• Error-free algorithm and architecture of radix-10 logarithmic converter
• Table driven Newton scheme for high precision logarithm generation
• Error analysis of the Kmetz/Maenner algorithm
• A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor

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