Vinod Viswanath
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Person:4564223
List of research outcomes
This list is not complete and representing at the moment only items from zbMATH Open and arXiv. We are working on additional sources - please check back here soon!
| Publication | Date of Publication | Type |
|---|---|---|
| Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems IEEE Transactions on Computers | 2018-06-12 | Paper |
Research outcomes over time
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