Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

DOI10.1109/TC.2007.1073MaRDI QIDQ4564225zbMATH OpenFDO

Authors Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham

Publication date 12 June 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2007.1073

Mathematics Subject Classification ID

Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30) Analytic circuit theory (94C05)

Cited in

(2)

• Formal Verification of Integer Multiplier Circuits Using Algebraic Reasoning: A Survey
• GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools

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