Won-Young Lee
From MaRDI portal
Person:5010434
Available identifiers
zbMath Open lee.won-youngMaRDI QIDQ5010434
List of research outcomes
 | This list is not complete and representing at the moment only items from zbMATH Open and arXiv. We are working on additional sources - please check back here soon! |
| Publication | Date of Publication | Type |
|---|---|---|
| A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation | 2021-08-26 | Paper |
| A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme | 2021-08-26 | Paper |
Research outcomes over time
This page was built for person: Won-Young Lee
