Pipelining architecture of AES encryption and key generation with search based memory

DOI10.1007/978-3-642-14478-3_23MaRDI QIDQ3164605zbMATH OpenOpenAlexFDO

Authors T. Subashri, Ramanathan Arunachalam, B. Gokul Vinoth Kumar, V. Vaidehi

Publication date 28 October 2010

Published in Recent Trends in Network Security and Applications (Search for Journal in Brave)

Full work available at URL https://zenodo.org/record/1244058

zbMATH Keywords

AES pipeliningkey pipeliningsearch based memoryVLSI

Mathematics Subject Classification ID

Computer system organization (68M99) Data encryption (aspects in computer science) (68P25)

Recommendations

• S-box pipelining using genetic algorithms for high-throughput AES implementations: how fast can we go?
• A Versatile Pipelined Hardware Implementation for Encryption and Decryption Using Advanced Encryption Standard
• PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
• scientific article; zbMATH DE number 2081069
• Rijndael FPGA implementations utilising look-up tables

Cited in

(3)

• A fault-tolerant pipelined architecture for symmetric block ciphers
• Extreme pipelining towards the best area-performance trade-off in hardware
• S-box pipelining using genetic algorithms for high-throughput AES implementations: how fast can we go?

This page was built for publication: Pipelining architecture of AES encryption and key generation with search based memory

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3164605)