Project verification and construction of superchip tests at the RTL level

DOI10.1134/S0005117913010104MaRDI QIDQ384503zbMATH OpenFDO

Authors L. A. Zolotorevich

Publication date 27 November 2013

Published in Automation and Remote Control (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1134/S0005117913010104

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

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Cites work

• Development of tests for VLSI circuit testability at the upper design levels

Cited in

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• Development of tests for VLSI circuit testability at the upper design levels

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