Using mappings to prove timing properties

DOI10.1007/BF02252683zbMath0773.68054OpenAlexW2043695863MaRDI QIDQ1200918

Nancy A. Lynch, Hagit Attiya

Publication date: 16 January 1993

Published in: Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf02252683

zbMATH Keywords

safetytimed automataI/O automataconcurrent algorithmsassertional reasoningpossibilities mappingsprogress functionstime propertiestiming-based algorithms

Mathematics Subject Classification ID

Modes of computation (nondeterministic, parallel, interactive, probabilistic, etc.) (68Q10) Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (11)

Hybrid diagrams: A deductive-algorithmic approach to hybrid system verification ⋮ Time-Bounded Verification ⋮ A theory of implementation and refinement in timed Petri nets ⋮ Efficiency of semisynchronous versus asynchronous networks ⋮ Verifying abstractions of timed systems ⋮ Using mappings to prove timing properties ⋮ What good are digital clocks? ⋮ Action transducers and timed automata ⋮ Event-clock automata: a determinizable class of timed automata ⋮ On a class of timer hybrid systems reducible to finite state automata ⋮ Hybrid diagrams

Cites Work

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• Real-time logics: Complexity and expressiveness
• The existence of refinement mappings
• Calculi for synchrony and asynchrony
• Using mappings to prove timing properties
• A framework for real-time discrete event control
• Specifying Concurrent Program Modules
• A Graph-Theoretic Approach for Timing Analysis and its Implementation

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