Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers
DOI10.1016/0167-8191(92)90058-FzbMATH Open0795.68014OpenAlexW2091594747MaRDI QIDQ1201940FDOQ1201940
Authors: Marius V. A. Hancu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie 
Publication date: 17 January 1993
Published in: Parallel Computing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/0167-8191(92)90058-f
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- scientific article; zbMATH DE number 2033521
parallel computingrouting algorithmsignature analysiscontrol flow checkingaliasing probabilityconcurrent testingdata dependence checkingmassively-parallel computerson-line error-detectionpacket-switched routingsystem-level error detection
Reliability, testing and fault tolerance of networks and computer systems (68M15) Distributed algorithms (68W15) Mathematical problems of computer architecture (68M07)
Cited In (4)
- Fault detection in multiprocessor systems and array processors
- On-line control flow error detection using relationship signatures among basic blocks
- Utilization of on-line (concurrent) checkers during built-in self-test and vice versa
- Test-based diagnosis of faults in data exchange addressing in computer systems using parallel model
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