Utilization of on-line (concurrent) checkers during built-in self-test and vice versa
DOI10.1109/12.481487zbMATH Open1049.68515OpenAlexW2167126021MaRDI QIDQ4420909FDOQ4420909
Authors: Sandeep K. Gupta, Dhiraj K. Pradhan
Publication date: 1996
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://semanticscholar.org/paper/9ec3260da50311bbc9bf5a6fbbb7b318545b7975
Recommendations
- Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers
- New structures of the concurrent error detection systems for logic circuits
- A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing
- On-line error detection and fast recover techniques for dependable embedded processors
- A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
Reliability, testing and fault tolerance of networks and computer systems (68M15) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)
Cited In (4)
This page was built for publication: Utilization of on-line (concurrent) checkers during built-in self-test and vice versa
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4420909)