New structures of the concurrent error detection systems for logic circuits
DOI10.1134/S0005117917020096zbMATH Open1362.94072OpenAlexW2586174556MaRDI QIDQ2397271FDOQ2397271
Authors: V. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov, V. V. Dmitriev 
Publication date: 22 May 2017
Published in: Automation and Remote Control (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1134/s0005117917020096
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Cites Work
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- A note on error detection codes for asymmetric channels
- Summation codes for organization of control of combinational circuits
- Code Design for Dependable Systems
- On summation code properties in functional control circuits
- Self-checking checkers for balanced codes
- A modified summation code for organizing control of combinatorial circuits
- Checking of combinational circuits basing on modification sum codes
- Necessary and sufficient conditions for the synthesis of completely testable modulo 2 convolution circuits
- Self-checking computer circuits and systems (review)
- On codes with summation of data bits in concurrent error detection systems
Cited In (12)
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- Logical Aspects of Computational Linguistics
- Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation
- Utilization of on-line (concurrent) checkers during built-in self-test and vice versa
- Synthesis of self-checking combination devices based on allocating special groups of outputs
- Fault-tolerant systems with concurrent error-locating capability
- Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices
- Malyugin's theorems: A new concept in logical control, VLSI design, and data structures for new technologies
- Error Tolerant Design of Multivalued Logic Functions
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