New structures of the concurrent error detection systems for logic circuits

DOI10.1134/S0005117917020096MaRDI QIDQ2397271zbMATHOpenAlexFDO

Authors V. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov, V. V. Dmitriev

Publication date 22 May 2017

Published in Automation and Remote Control (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1134/s0005117917020096

zbMATH Keywords

areaduplicationrealization complexityinformation vectorparity codeberger codecode with summation of weighted transitionsconcurrent error detection systemoptimal code with summation

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

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Cites work

• A modified summation code for organizing control of combinatorial circuits
• A note on error detection codes for asymmetric channels
• Applications of modular summation codes to concurrent error detection systems for combinational Boolean circuits
• Checking of combinational circuits basing on modification sum codes
• Code Design for Dependable Systems
• Necessary and sufficient conditions for the synthesis of completely testable modulo 2 convolution circuits
• On codes with summation of data bits in concurrent error detection systems
• On summation code properties in functional control circuits
• Self-checking checkers for balanced codes
• Self-checking computer circuits and systems (review)
• Summation codes for organization of control of combinational circuits

Cited in

(16)

• Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation
• Applications of modular summation codes to concurrent error detection systems for combinational Boolean circuits
• A single parity-check digit for one trit error detection in ternary communication systems: gate-level and transistor-level designs
• scientific article; zbMATH DE number 177872 (Why is no real title available?)
• Error Tolerant Design of Multivalued Logic Functions
• Fault-tolerant systems with concurrent error-locating capability
• scientific article; zbMATH DE number 4023203 (Why is no real title available?)
• On codes with summation of data bits in concurrent error detection systems
• A systematic approach for designing concurrent error-detecting systolic arrays using redundancy
• Logical Aspects of Computational Linguistics
• Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code
• Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices
• Malyugin's theorems: A new concept in logical control, VLSI design, and data structures for new technologies
• scientific article; zbMATH DE number 4006162 (Why is no real title available?)
• Utilization of on-line (concurrent) checkers during built-in self-test and vice versa
• Synthesis of self-checking combination devices based on allocating special groups of outputs

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