On codes with summation of data bits in concurrent error detection systems
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Publication:2261788
DOI10.1134/S0005117914080098zbMath1307.94135OpenAlexW2022939629MaRDI QIDQ2261788
V. V. Sapozhnikov, Vl. V. Sapozhnikov, A. A. Blyudov, D. V. Efanov
Publication date: 13 March 2015
Published in: Automation and Remote Control (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1134/s0005117914080098
Related Items (4)
New structures of the concurrent error detection systems for logic circuits ⋮ Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code ⋮ Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices ⋮ Sum codes with fixed values of multiplicities for detectable unidirectional and asymmetrical errors for technical diagnostics of discrete systems
Cites Work
- Summation codes for organization of control of combinational circuits
- On summation code properties in functional control circuits
- Logic complement, a new method of checking the combinational circuits
- A modified summation code for organizing control of combinatorial circuits
- A note on error detection codes for asymmetric channels
- Optimal error detection codes for completely asymmetric binary channels
- Systematic Unidirectional Error-Detecting Codes
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