| Publication | Date of Publication | Type |
|---|
| Boolean-complement based fault-tolerant electronic device architectures | 2021-11-26 | Paper |
| Sum codes with fixed values of multiplicities for detectable unidirectional and asymmetrical errors for technical diagnostics of discrete systems | 2020-01-27 | Paper |
| Synthesis of self-checking combination devices based on allocating special groups of outputs | 2018-11-05 | Paper |
| Sum codes with efficient detection of twofold errors for organization of concurrent error-detection systems of logical devices | 2018-10-17 | Paper |
| Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code | 2017-08-24 | Paper |
| New structures of the concurrent error detection systems for logic circuits | 2017-05-22 | Paper |
| Applications of modular summation codes to concurrent error detection systems for combinational Boolean circuits | 2016-04-15 | Paper |
| A modified summation code for organizing control of combinatorial circuits | 2015-03-13 | Paper |
| On codes with summation of data bits in concurrent error detection systems | 2015-03-13 | Paper |
| Summation codes for organization of control of combinational circuits | 2014-10-15 | Paper |
| On summation code properties in functional control circuits | 2011-01-03 | Paper |
| Checking of combinational circuits basing on modification sum codes | 2009-02-26 | Paper |
| Checking combinational circuits by the method of logic complement | 2005-12-19 | Paper |
| Self-dual self-testing multicycle circuits: Their properties | 2005-06-17 | Paper |
| Logic complement, a new method of checking the combinational circuits | 2005-06-17 | Paper |
| A functional fault-detection self-test for combinational circuits | 2004-10-18 | Paper |
| Detection of faults in combinational circuits by a self-dual test | 2004-10-13 | Paper |
| Self-testing combinational circuits: their design through the use of the properties of self-dual functions | 2004-10-13 | Paper |
| Study of combinational self-checking devices with independent and monotonic independent outputs | 1999-05-03 | Paper |
| A self-checking comparator with additional pulse input | 1999-03-16 | Paper |
| Construction of combinational self-checking devices with monotonically independent outputs | 1996-06-12 | Paper |
| Methods for providing safety in discrete systems | 1996-05-27 | Paper |
| Self-checking checkers for balanced codes | 1994-03-22 | Paper |
| Design of self-checking checkers for 1-out-of-3 codes | 1992-06-27 | Paper |
| Interpreter program implementation of self-checking testers | 1992-06-25 | Paper |
| Error detection in software-implemented self-checking testers in microprocessor-based systems | 1992-06-25 | Paper |
| Design of high-speed checkers for Berger codes | 1989-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4204113 | 1989-01-01 | Paper |
| Design of maximum-speed self-checking m-out-of-n checkers | 1988-01-01 | Paper |
| Synthesis of self-checking checkers for codes with addition | 1986-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3731530 | 1985-01-01 | Paper |
| Properties of bridging faults in combinational circuits | 1984-01-01 | Paper |
| Universal algorithm for synthesizing self-checking testers for constant- weight codes | 1984-01-01 | Paper |
| Universal synthesis algorithm for 1/n testers | 1983-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3318118 | 1982-01-01 | Paper |
| Properties of multiple faults in logic circuits with contacts | 1981-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3962925 | 1981-01-01 | Paper |
| Synthesis of self-checking testers in automata with fault detection | 1980-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3908957 | 1980-01-01 | Paper |
| Synthesis of totally self-checking asynchronous automata | 1979-01-01 | Paper |
| Class of easily checkable combinational circuits | 1979-01-01 | Paper |
| Check of linear combination circuits | 1979-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3852119 | 1979-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3904533 | 1979-01-01 | Paper |
| Contact circuit monitoring | 1978-01-01 | Paper |
| Fault relations in combinational logic networks | 1978-01-01 | Paper |
| Design of asynchronous finite automata with fault detection | 1977-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4175191 | 1977-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4184339 | 1977-01-01 | Paper |
| Algorithm to design an equivalent normal form | 1976-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4083337 | 1976-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4110942 | 1976-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4154496 | 1975-01-01 | Paper |
| Reduction of the list of single faults in the design of tests for combinational circuits | 1974-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4071170 | 1973-01-01 | Paper |
| On the synthesis of finite automata with exclusion of dangerous failures | 1972-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q5655298 | 1972-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q5631003 | 1971-01-01 | Paper |
