Boolean-complement based fault-tolerant electronic device architectures

DOI10.1134/S0005117921080075MaRDI QIDQ2052593zbMATH OpenOpenAlexFDO

Authors D. V. Efanov, V. V. Sapozhnikov, Vl. V. Sapozhnikov

Publication date 26 November 2021

Published in Automation and Remote Control (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1134/s0005117921080075

zbMATH Keywords

Boolean complement methodcombinational circuitDMR architecture with computation checkingerror correction with parity code checkingfault-tolerant architectureTMR architecture

Mathematics Subject Classification ID

Switching theory, applications of Boolean algebras to circuits and networks (94C11)

Recommendations

• scientific article; zbMATH DE number 4187722
• On the design of reliable Boolean circuits that contain partially unreliable gates
• scientific article; zbMATH DE number 850403
• On self-correcting logic circuits of unreliable gates with at most two inputs
• On self-correcting logic circuits of unreliable gates

Cites work

• Analysis of reliability characteristics of self-checkable redundant structures
• Checking combinational circuits by the method of logic complement
• Code Design for Dependable Systems
• Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's code
• Fault-tolerant computer-aided control systems with multiversion-threshold adaptation: adaptation methods, reliability estimation, and choice of an architecture
• scientific article; zbMATH DE number 3425520 (Why is no real title available?)
• Method of synthesizing built-in monitoring arrangements for automata with memory
• Models and properties of multialternative fault-tolerant systems
• Necessary and sufficient conditions for the synthesis of completely testable modulo 2 convolution circuits
• Sum codes with fixed values of multiplicities for detectable unidirectional and asymmetrical errors for technical diagnostics of discrete systems
• Survivability estimate for multilevel majorized redundancy systems under pulse-type unfavorable factors
• Synthesis of self-checking combination devices based on allocating special groups of outputs

This page was built for publication: Boolean-complement based fault-tolerant electronic device architectures

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2052593)