A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing

DOI10.1109/TC.1984.1676486MaRDI QIDQ3321995zbMATH OpenOpenAlexFDO

Authors Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka

Publication date 1984

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1984.1676486

zbMATH Keywords

self-verificationfault-detectionself-testingerror-detectionbuilt-in testingerror-checking logicerror-checking scheme for multioutput combinational circuitsgroup-parity prediction checkerself- checking checker

Mathematics Subject Classification ID

Recommendations

• A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing
• Study of combinational self-checking devices with independent and monotonic independent outputs
• Construction of code-disjoint self-parity combinational circuits for self-testing and functional diagnosis
• Logic complement, a new method of checking the combinational circuits
• Synthesis of self-checking combination devices based on allocating special groups of outputs

Cited in

(6)

• Multiple fault detection in parity checkers
• Checking of combinational circuits basing on modification sum codes
• New Self-Checking Booth Multipliers
• Checking combinational circuits by the method of logic complement
• A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing
• Utilization of on-line (concurrent) checkers during built-in self-test and vice versa

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