A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing

DOI10.1109/TC.1984.1676486zbMATH Open0536.94019OpenAlexW1913632539MaRDI QIDQ3321995FDOQ3321995

Authors: Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka 

Publication date: 1984

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1984.1676486

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zbMATH Keywords

self-verificationfault-detectionself-testingerror-detectionbuilt-in testingerror-checking logicerror-checking scheme for multioutput combinational circuitsgroup-parity prediction checkerself- checking checker

Mathematics Subject Classification ID

Cited In (6)

• Checking combinational circuits by the method of logic complement
• Utilization of on-line (concurrent) checkers during built-in self-test and vice versa
• Checking of combinational circuits basing on modification sum codes
• New Self-Checking Booth Multipliers
• A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing
• Multiple fault detection in parity checkers

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