Timing diagrams: Formalization and algorithmic verification

DOI10.1023/A:1008345113376MaRDI QIDQ1306169zbMATH OpenFDO

Authors Kathi Fisler

Publication date 22 September 1999

Published in Journal of Logic, Language and Information (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/A:1008345113376

zbMATH Keywords

\(\omega\)-regular languagesBüchi automatacomputer-aided verificationhardware designlanguage containmentmodel checkingreversal bounded counter machine languagestiming diagram logic

Mathematics Subject Classification ID

Decidability of theories and sets of sentences (03B25) Logic in computer science (03B70) Automata and formal grammars in connection with logical questions (03D05) Mathematical problems of computer architecture (68M07) Specification and verification (program logics, model checking, etc.) (68Q60)

Cited in

(10)

• The Verus language: Representing time efficiently with BDDs
• Formal verification of timed synchronous dataflow graphs using Lustre
• Reasoning about synchronization in GALS systems
• scientific article; zbMATH DE number 139824 (Why is no real title available?)
• scientific article; zbMATH DE number 2079808 (Why is no real title available?)
• scientific article; zbMATH DE number 791802 (Why is no real title available?)
• Correct Hardware Design and Verification Methods
• Towards diagrammability and efficiency in event sequence languages
• A graphic language based on timing diagrams
• Proving sequential function chart programs using timed automata

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