A method for minimization design of two-level-logic networks using multiplexer universal logic modules

DOI10.1007/BF02939490zbMath0809.94039OpenAlexW2018106661MaRDI QIDQ1322397

Wenbin Jiang

Publication date: 4 July 1994

Published in: Journal of Computer Science and Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf02939490

zbMATH Keywords

logic designcombinational networkcombinational functionsminimization designmultiplexer realization

Mathematics Subject Classification ID

Analytic circuit theory (94C05) Applications of design theory to circuits and networks (94C30)

Cites Work

• Modular decomposition of combinatorial multiple-values circuits
• On the Minimization of Tree-Type Universal Logic Circuits
• ULM Implicants for Minimization of Univers Logic Module Circuits

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