A method for minimization design of two-level-logic networks using multiplexer universal logic modules

DOI10.1007/BF02939490MaRDI QIDQ1322397zbMATH OpenOpenAlexFDO

Authors Wenbin Jiang

Publication date 4 July 1994

Published in Journal of Computer Science and Technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf02939490

zbMATH Keywords

combinational networklogic designcombinational functionsminimization designmultiplexer realization

Mathematics Subject Classification ID

Analytic circuit theory (94C05) Applications of design theory to circuits and networks (94C30)

Recommendations

• scientific article; zbMATH DE number 1737504
• scientific article; zbMATH DE number 3685410
• scientific article; zbMATH DE number 3902554
• scientific article; zbMATH DE number 3570350
• Two-level logic minimization: an overview

Cites work

• Modular decomposition of combinatorial multiple-values circuits
• On the Minimization of Tree-Type Universal Logic Circuits
• ULM Implicants for Minimization of Univers Logic Module Circuits

Cited in

(6)

• scientific article; zbMATH DE number 6027974 (Why is no real title available?)
• scientific article; zbMATH DE number 3570350 (Why is no real title available?)
• scientific article; zbMATH DE number 4025344 (Why is no real title available?)
• scientific article; zbMATH DE number 3685410 (Why is no real title available?)
• scientific article; zbMATH DE number 3900682 (Why is no real title available?)
• ULM Implicants for Minimization of Univers Logic Module Circuits

This page was built for publication: A method for minimization design of two-level-logic networks using multiplexer universal logic modules

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1322397)