On the Minimization of Tree-Type Universal Logic Circuits

DOI10.1109/T-C.1975.224141zbMATH Open0316.94032OpenAlexW1997420068MaRDI QIDQ4077907FDOQ4077907

Authors: Chris C. Cheung, Roger W. Ehrich 

Publication date: 1975

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/t-c.1975.224141

Mathematics Subject Classification ID

Cited In (1)

• A method for minimization design of two-level-logic networks using multiplexer universal logic modules

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