Processor-time tradeoffs under bounded-speed message propagation. I: Upper bounds

DOI10.1007/S002240000066MaRDI QIDQ1384682zbMATH OpenOpenAlexFDO

Authors Gianfranco Bilardi, F. P. Preparata

Publication date 25 May 1998

Published in Theory of Computing Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s002240000066

zbMATH Keywords

simulations of multiprocessor machinestopological separator

Mathematics Subject Classification ID

Computer system organization (68M99)

Recommendations

• Processor-time tradeoffs under bounded-speed message propagation. II: Lower bounds
• Lower bounds to processor-time tradeoffs under bounded-speed message propagation
• Processor-time tradeoffs in PRAM simulations

Cited in

(4)

• Processor-time tradeoffs under bounded-speed message propagation. II: Lower bounds
• Processor-Ring Communication: A Tight Asymptotic Bound on Packet Waiting Times
• Lower bounds to processor-time tradeoffs under bounded-speed message propagation
• The cache complexity of multithreaded cache oblivious algorithms

This page was built for publication: Processor-time tradeoffs under bounded-speed message propagation. I: Upper bounds

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1384682)