Upper bound on the number of processors for scheduling with interprocessor communication delays.

DOI10.1007/S001860000062zbMATH Open1038.90036OpenAlexW2001561787MaRDI QIDQ1403166FDOQ1403166

Authors: A. Moukrim 

Publication date: 2000

Published in: Mathematical Methods of Operations Research (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s001860000062

Recommendations

• On the minimum number of processors for scheduling problems with communication delays
• UET scheduling with unit interprocessor communication delays
• Scheduling Precedence Graphs in Systems with Interprocessor Communication Times
• Task scheduling with and without communication delays: A unified approach
• Scheduling in the presence of processor networks : complexity and approximation

zbMATH Keywords

schedulingmakespancommunication delaysminimum number of processors

Mathematics Subject Classification ID

Deterministic scheduling theory in operations research (90B35) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Cited In (3)

• Processor-Ring Communication: A Tight Asymptotic Bound on Packet Waiting Times
• A note on Graham's bound
• Minimizing the number of machines for minimum length schedules

This page was built for publication: Upper bound on the number of processors for scheduling with interprocessor communication delays.

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1403166)