Computing with pipelined block transfer
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Publication:1817502
DOI10.1007/BF02575875zbMATH Open0861.68028OpenAlexW1994923138MaRDI QIDQ1817502FDOQ1817502
Authors: M. Spuri
Publication date: 8 December 1996
Published in: Calcolo (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/bf02575875
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Cites Work
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- A parallel algorithm for constructing minimum spanning trees
- Algorithms for parallel memory. II: Hierarchical multilevel memories
- A model of computation for VLSI with related complexity results
- A model of sequential computation with Pipelined access to memory
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