Parallel prefix computation on extended multi-mesh network.
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Publication:1853159
DOI10.1016/S0020-0190(02)00317-4zbMath1042.68126MaRDI QIDQ1853159
Shailendra Kumar, B. Damodara Naidu, Bhabani P. Sinha, Prasanta K. Jana, Monish Arora
Publication date: 21 January 2003
Published in: Information Processing Letters (Search for Journal in Brave)
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Cites Work
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- Limited width parallel prefix circuits
- Faster optimal parallel prefix sums and list ranking
- Depth-size trade-offs for parallel prefix computation
- Parallel Prefix Computation
- Parallel Solution of Recurrence Problems
- A new network topology with multiple meshes
- OPTIMAL PARALLEL PREFIX ON MESH ARCHITECTURES
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