Limited width parallel prefix circuits

DOI10.1007/BF00127876zbMATH Open1215.94093OpenAlexW2028539866MaRDI QIDQ547485FDOQ547485

Authors David A. Carlson, Binay Sugla 

Publication date 2 July 2011

Published in The Journal of Supercomputing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf00127876

Mathematics Subject Classification ID

Complexity and performance of numerical algorithms (65Y20) Analytic circuit theory (94C05) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cites Work

• scientific article; zbMATH DE number 3214539 (Why is no real title available?)
• A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
• A Regular Layout for Parallel Adders
• Adapting shuffle-exchange like parallel processing organizations to work as systolic arrays
• An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines
• Depth-size trade-offs for parallel prefix computation
• Efficient parallel algorithms for linear recurrence computation
• On measures of information and their characterizations
• Optimal algorithms for parallel polynomial evaluation
• Parallel Prefix Computation
• Size-time complexity of Boolean networks for prefix computations
• Time and Parallel Processor Bounds for Linear Recurrence Systems

Cited In (3)

• Parallel prefix computation on extended multi-mesh network.
• On a class of cell circuits
• Minimal parallel prefix circuits

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