A Regular Layout for Parallel Adders

DOI10.1109/TC.1982.1675982zbMath0477.94037OpenAlexW2168543008WikidataQ55953421 ScholiaQ55953421MaRDI QIDQ3934311

H. T. Kung, Richard P. Brent

Publication date: 1982

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1982.1675982

zbMATH Keywords

VLSI architecturecombinational logicprefix computationmodels of computationparallel additioncircuit designarea-time complexityparallel polynomial evaluationcarry lookahead

Mathematics Subject Classification ID

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