Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

DOI10.1016/0020-0190(93)90203-LzbMATH Open0770.68063OpenAlexW2085287525MaRDI QIDQ1802064FDOQ1802064

Authors: P. Thangavel, V. P. Muthuswamy 

Publication date: 20 September 1993

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(93)90203-l

Recommendations

• Publication:5753513
• Parallel matrix multiplication on a linear array with a reconfigurable pipelined bus system
• Fast parallel algorithms for binary multiplication and their implementation on systolic architectures
• scientific article; zbMATH DE number 3856402
• Publication:4725742
• Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system
• Parallel algorithms and architectures for matrix multiplication
• Parallel evaluation of arithmetic circuits

zbMATH Keywords

addition of two \(n\)-bit numbersmultiplication of two \(n\)-bit binary numbersPARBS

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Distributed algorithms (68W15)

Cites Work

• A Regular Layout for Parallel Adders
• Constant time sorting on a processor array with a reconfigurable bus system
• A Two's Complement Parallel Array Multiplication Algorithm
• Combinational Circuit Synthesis with Time and Component Bounds
• Fast one's-complement multiplication
• Algorithms for Iterative Array Multiplication
• A Way to Build Efficient Carry-Skip Adders
• A Compact High-Speed Parallel Multiplication Scheme

Cited In (9)

• Scaling multiple addition and prefix sums on the reconfigurable mesh.
• Algorithms for Iterative Array Multiplication
• Bit serial addition trees and their applications
• Construction of algorithms for parallel addition in expanding bases via extending window method
• Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system
• Integer summing algorithms on reconfigurable meshes
• \(k\)-block parallel addition versus 1-block parallel addition in non-standard numeration systems
• Title not available (Why is that?)
• Title not available (Why is that?)

This page was built for publication: Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1802064)