Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems

DOI10.1016/0020-0190(93)90203-LMaRDI QIDQ1802064zbMATHOpenAlexFDO

Authors P. Thangavel, V. P. Muthuswamy

Publication date 20 September 1993

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0020-0190(93)90203-l

zbMATH Keywords

addition of two \(n\)-bit numbersmultiplication of two \(n\)-bit binary numbersPARBS

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Distributed algorithms (68W15)

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Cites work

• A Compact High-Speed Parallel Multiplication Scheme
• A Regular Layout for Parallel Adders
• A Two's Complement Parallel Array Multiplication Algorithm
• A Way to Build Efficient Carry-Skip Adders
• Algorithms for Iterative Array Multiplication
• Combinational Circuit Synthesis with Time and Component Bounds
• Constant time sorting on a processor array with a reconfigurable bus system
• Fast one's-complement multiplication

Cited in

(9)

• Construction of algorithms for parallel addition in expanding bases via extending window method
• scientific article; zbMATH DE number 3958734 (Why is no real title available?)
• \(k\)-block parallel addition versus 1-block parallel addition in non-standard numeration systems
• Scaling multiple addition and prefix sums on the reconfigurable mesh.
• Integer summing algorithms on reconfigurable meshes
• Algorithms for Iterative Array Multiplication
• Bit serial addition trees and their applications
• Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system
• scientific article; zbMATH DE number 3939261 (Why is no real title available?)

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