A class of almost-optimal size-independent parallel prefix circuits
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Publication:2443006
DOI10.1016/J.JPDC.2013.03.012zbMath1284.94163OpenAlexW2085318004MaRDI QIDQ2443006
Publication date: 2 April 2014
Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/j.jpdc.2013.03.012
Cites Work
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- Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system
- Faster optimal parallel prefix circuits: new algorithmic construction
- The parallel complexity of integer prefix summation
- Faster optimal parallel prefix sums and list ranking
- A new approach to constructing optimal parallel prefix circuits with small depth
- Parallel tree contraction and prefix computations on a large family of interconnection topologies
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