Constructing H4, a fast depth-size optimal parallel prefix circuit
From MaRDI portal
Publication:1402306
DOI10.1023/A:1022084814175zbMATH Open1039.68096OpenAlexW1553034866MaRDI QIDQ1402306FDOQ1402306
Authors: Yen-Chun Lin, Yao-Hsien Hsu, Chun-Keng Liu 
Publication date: 20 August 2003
Published in: The Journal of Supercomputing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1023/a:1022084814175
Recommendations
- A new class of depth-size optimal parallel prefix circuits
- A new approach to constructing optimal parallel prefix circuits with small depth
- Faster optimal parallel prefix circuits: new algorithmic construction
- A class of almost-optimal size-independent parallel prefix circuits
- scientific article; zbMATH DE number 2065716
- Depth-size trade-offs for parallel prefix computation
- On the complexity of parallelizing sequential circuits using the parallel-prefix method
- scientific article; zbMATH DE number 1307000
- scientific article; zbMATH DE number 3852437
- On the power of homogeneous depth 4 arithmetic circuits
Cited In (10)
- Parallel Prefix Computation
- Finding optimal parallel prefix circuits with fan-out 2 in constant time
- Limited width parallel prefix circuits
- A new approach to constructing optimal parallel prefix circuits with small depth
- A new class of depth-size optimal parallel prefix circuits
- Faster optimal parallel prefix circuits: new algorithmic construction
- A class of almost-optimal size-independent parallel prefix circuits
- Depth-size trade-offs for parallel prefix computation
- Title not available (Why is that?)
- Functional and dynamic programming in the design of parallel prefix networks
This page was built for publication: Constructing \(H\)4, a fast depth-size optimal parallel prefix circuit
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1402306)
